BSI PD ISO/PAS 19451-1:2016:2018 Edition
$215.11
Application of ISO 26262:2011-2012 to semiconductors – Application of concepts
| Published By | Publication Date | Number of Pages |
| BSI | 2018 | 138 |
This document is applicable to developers who are evaluating the use of semiconductor components or parts in hardware components, systems, or items developed according to ISO 26262.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 8 | Foreword |
| 9 | Introduction |
| 10 | 1 Scope 2 Normative references 3 Terms and definitions |
| 11 | 4 Symbols and abbreviated terms |
| 13 | 5 Analogue/mixed signal components and ISO 26262 5.1 About analogue and mixed signal components |
| 14 | 5.2 Analogue and mixed signal components and failure modes 5.2.1 About failure modes |
| 22 | 5.2.2 About safe faults |
| 23 | 5.2.3 About transient faults 5.3 Notes about safety analysis 5.3.1 General 5.3.2 Level of granularity of analysis |
| 24 | 5.3.3 Examples of usage of failure mode distributions |
| 25 | 5.3.4 Example of failure rates estimation for an analogue part |
| 26 | 5.3.5 Example of safety metrics computation |
| 40 | 5.3.6 Dependent failures analysis 5.3.7 Verification of architectural metrics computation |
| 41 | 5.4 Examples of safety mechanisms |
| 42 | 5.4.1 Resistive pull up/down 5.4.2 Over and under voltage monitoring |
| 43 | 5.4.3 Voltage clamp (limiter) 5.4.4 Over-current monitoring 5.4.5 Current limiter 5.4.6 Power on reset 5.4.7 Analogue watchdog |
| 44 | 5.4.8 Filter 5.4.9 Thermal monitor 5.4.10 Analogue Built-in Self-Test (Analogue BIST) 5.4.11 ADC monitoring 5.4.12 ADC attenuation detection 5.4.13 Stuck on ADC channel detection |
| 45 | 5.5 About avoidance of systematic faults during the development phase |
| 48 | 5.6 About safety documentation 6 Intellectual property and ISO 26262 6.1 About intellectual property 6.1.1 Understanding intellectual property |
| 49 | 6.1.2 Types of intellectual property |
| 50 | 6.2 Safety requirements for intellectual property |
| 52 | 6.3 Intellectual property lifecycle 6.3.1 ISO 26262 and the intellectual property lifecycle |
| 53 | 6.3.2 Intellectual property as safety element out of context (SEooC) |
| 54 | 6.3.3 Intellectual property designed in context 6.3.4 Intellectual property use through hardware component qualification 6.3.5 Intellectual property use through proven in use argument 6.4 Work products for intellectual property 6.4.1 ISO 26262 and work products for intellectual property 6.4.2 Safety plan |
| 55 | 6.4.3 Safety requirements and verification review of the IP design 6.4.4 Safety analysis report 6.4.5 Analysis of dependent failures 6.4.6 Confirmation measure reports |
| 56 | 6.4.7 Development interface agreement 6.4.8 Integration documentation set |
| 57 | 6.5 Integration of black-box intellectual property |
| 58 | 7 Multi-core components and ISO 26262 7.1 Types of MC components 7.2 Implications of ISO 26262 on MC components 7.2.1 Introduction |
| 59 | 7.2.2 ASIL decomposition in MC components |
| 61 | 7.2.3 Coexistence of elements with different ASILs in MC components |
| 62 | 7.2.4 Freedom from interference (FFI) in MC components 7.2.5 Software partitioning in MC components |
| 63 | 7.2.6 Dependent failures in MC component 7.2.7 Timing requirements in MC component |
| 64 | 8 Programmable logic devices and ISO 26262 8.1 About programmable logic devices 8.1.1 General |
| 65 | 8.1.2 About PLD types |
| 66 | 8.1.3 ISO 26262 Lifecycle mapping to PLD |
| 69 | 8.2 Fault models and failure modes of PLD |
| 70 | 8.3 Notes about safety analyses for PLDs 8.3.1 Quantitative analysis for a PLD |
| 74 | 8.3.2 Dependent failure analysis for a PLD |
| 76 | 8.4 Examples of safety mechanisms for PLD |
| 77 | 8.5 Avoidance of systematic faults for PLD 8.5.1 Avoiding systematic faults in the implementation of PLD 8.5.2 About PLD supporting tools 8.5.3 Avoiding systematic faults for PLD users |
| 79 | 8.6 Safety documentation for a PLD |
| 80 | 8.7 Example of safety analysis for PLD 8.7.1 Architecture of the example |
| 81 | 8.7.2 PLD external measures |
| 82 | 8.7.3 PLD internal measures |
| 86 | 9 Base failure rate estimation and ISO 26262 (all parts) 9.1 About base failure rate estimation 9.1.1 Impact of failure mechanisms on base failure rate estimation 9.1.2 Considerations in base failure rate estimation for functional safety |
| 87 | 9.1.3 Techniques for base failure rate estimation 9.1.4 Documentation on the assumptions for base failure rate calculation |
| 88 | 9.2 (General) clarifications on terms 9.2.1 Clarification of transient fault quantification |
| 89 | 9.2.2 Clarification on component package failure rate 9.2.3 Clarification on power-up and power-down times 9.3 Permanent base failure rate calculation methods 9.3.1 Permanent base failure rate calculation using industry sources |
| 97 | 9.3.2 Permanent base failure rate calculation using field data statistics |
| 100 | 9.3.3 Calculation example of hardware component failure rate |
| 103 | 9.3.4 Base failure rate calculation using accelerated life tests |
| 104 | 9.3.5 Failure rate distribution methods |
| 105 | 10 Semiconductor dependent failure analysis and ISO 26262 10.1 Introduction to DFA for semiconductors |
| 106 | 10.2 Relationship between DFA and safety analysis |
| 107 | 10.3 Dependent failure scenarios |
| 109 | 10.4 Distinction between cascading failures and common cause failures 10.5 Dependent failure initiators 10.5.1 Dependent failure initiator list |
| 115 | 10.5.2 Verification of mitigation measures |
| 116 | 10.6 DFA workflow |
| 118 | 10.6.1 DFA decision and identification of HW and SW elements (B1) 10.6.2 Identification of DFI (B2) 10.6.3 Sufficiency of insight provided by the available information on the effect of identified DFI (B3 and B4) |
| 119 | 10.6.4 Consolidation of list of relevant DFI (B5) 10.6.5 Identification of necessary safety measures to control or mitigate DFI (B6) 10.6.6 Sufficiency of insight provided by the available information on the defined mitigation measures (B7 and B8) 10.6.7 Consolidate list of safety measures (B9) 10.6.8 Evaluation of the effectiveness to control or to avoid the dependent failure (B10) |
| 120 | 10.6.9 Assessment of risk reduction sufficiency and if required improve defined measures (B11 and B12) 10.7 Examples of dependent failure analysis 10.7.1 Microcontroller example |
| 126 | 10.7.2 Analog example |
| 136 | Bibliography |
