IEC 60747-15:2010 gives the requirements for isolated power semiconductor devices excluding devices with incorporated control circuits. These requirements are additional to those given in other parts of IEC 60747 for the corresponding non-isolated power devices. The main changes with respect to previous edition are listed below. a) Clause 3, 4 and 5 were re-edited and some of them were combined to other sub clauses. b) Clause 6, 7 were re-edited as a part of “Measuring methods” with amendment of suitable addition and deletion. c) Clause 8 was amended by suitable addition and deletion. d) Annex C, D and Bibliography were deleted. This publication is to be read in conjunction with \/2.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 7<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4 Letter symbols 4.1 General 4.2 Additional subscripts\/symbols 4.3 List letter symbols <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 5 Essential ratings (limiting values) and characteristics 5.1 General 5.2 Ratings (limiting values) <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 5.3 Characteristics <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 6 Measurement methods 6.1 Verification of isolation voltage rating between terminals and base plate (Visol) Figures Figure 1 \u2013 Basic circuit diagram for isolation breakdown withstandvoltage test (\u201chigh pot test\u201d) with Visol <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 6.2 Methods of measurement <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figure 2 \u2013 Circuit diagram for measurement of parasitic inductances (Lp) <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 3 \u2013 Wave forms <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | Figure 4 \u2013 Circuit diagram for measurement of parasitic capacitance (Cp) <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Figure 5 \u2013 Cross-section of an isolated power devicewith reference points for temperature measurement of Tc and Ts <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 7 Acceptance and reliability 7.1 General requirements <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 7.2 List of endurance tests 7.3 Acceptance defining criteria 7.4 Type tests and routine tests Tables Table 1 \u2013 Endurance tests Table 2 \u2013 Acceptance defining characteristics for endurance and reliability tests <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Table 3 \u2013 Minimum type and routine tests for isolated power semiconductor devices <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Annex A (informative) Test method of peak case non-rupture current Figure A.1 \u2013 Circuit diagram for test of peak case non-rupture current ICNR <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Annex B (informative) Measuring method of the thickness of thermal compound paste Figure B.1 \u2013 Example of a measuring gauge for a layer of thermal compound paste of a thickness between 5 um and 150 um <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Discrete devices – Isolated power semiconductor devices<\/b><\/p>\n |