This Technical Report provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers\u2019 specifications.<\/p>\n
The terms \u201cuprating\u201d and \u201cthermal uprating\u201d are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in Clause 3. They were coined as shorthand references to a special case of methods commonly used in selecting components for circuit design.<\/p>\n
This technical report describes the methods and processes for implementing this special case.<\/p>\n
All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes: only a rigorous application of the overall approach.<\/p>\n
Even though the device is used at wider temperatures, the wider temperatures usage will be limited to those that do not compromise applications performance and reliability, particularly for devices with narrow feature size geometries (e.g., 90 nm and less). This technical report does not imply that applications use the device to function beyond the absolute maximum rating limits of the device specified by the original device manufacturer and assumes that:<\/p>\n
device usage outside the original device manufacturers\u2019 specified temperature ranges is done only when no reasonable alternative approach is available and is performed with appropriate justification;<\/p>\n<\/li>\n
if it is necessary to use devices outside the original device manufacturers\u2019 specified temperature ranges, it is done with documented and controlled processes that assure integrity of the equipment.<\/p>\n<\/li>\n<\/ul>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 3.2 Abbreviations 4 Selection provisions 4.1 General 4.2 Device selection, usage and alternatives 4.2.1 General <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 4.2.2 Alternatives 4.2.3 Device technology 4.2.4 Compliance with the electronic component management plan <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level) <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 4.3.4 Device uprating methods <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 4.3.5 Device reliability assurance <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 4.4 Device quality assurance in wider temperature ranges 4.4.1 General 4.4.2 Device parameter re-characterisation testing 4.4.3 Device parameter conformance testing 4.4.4 Higher assembly level testing <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 4.4.5 Semiconductor device change monitoring 4.4.6 Failure data collection and analysis 4.5 Documentation 4.6 Device identification <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Figure 1 \u2013 Flow chart for semiconductor devices in wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | Figure 2 \u2013 Report form for documenting device usage in wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Annex\u00a0A (informative)Device parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Figure A.1 \u2013 Parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | Figure A.2 \u2013 Flow diagram of parameter re-characterisation capability assurance process <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | Table A.1 \u2013 Example of sample size calculation <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Figure A.3 \u2013 Margin in electrical parameter measurement based on the results of the sample test <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | Figure A.4 \u2013 Schematic diagram of parameter limit modifications Table A.2 \u2013 Parameter re-characterisation example: SN74ALS244 Octal Buffer\/Driver <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Figure A.5 \u2013 Parameter re-characterisation device quality assurance <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | Figure A.6 \u2013 Schematic of outlier products that may invalidate sample testing <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | Figure A.7 \u2013 Example of intermediate peak of an electrical parameter: voltage feedback input threshold change for Motorola MC34261 power factor controller [4] <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Figure A.8 \u2013 Report form for documenting device parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | Annex\u00a0B (informative)Stress balancing <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Figure B.1 \u2013 Iso-TJ curve: the relationship between ambient temperature and dissipated power <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | Figure B.2 \u2013 Graph of electrical parameters versus dissipated power <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | Figure B.3 \u2013 Iso-TJ curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | Figure B.4 \u2013 Power versus frequency curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 42<\/td>\n | Figure B.5 \u2013 Flow chart for stress balancing <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | Figure B.6 \u2013 Report form for documenting stress balancing <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | Annex\u00a0C (informative)Parameter conformance assessment <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Figure C.1 \u2013 Relationship of temperature ratings, requirements and margins <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | Figure C.2 \u2013 Typical fallout distribution versus Treq-max <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | Figure C.3 \u2013 Parameter conformance assessment flow <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | Figure C.4 \u2013 Report form for documenting parameter conformance testing <\/td>\n<\/tr>\n | ||||||
| 51<\/td>\n | Annex\u00a0D (informative)Higher assembly level testing <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | Figure D.1 \u2013 Flow chart of higher level assembly testing <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | Figure D.2 \u2013 Report form for documenting higher level assembly test at temperature extremes <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | Bibliography Figures Tables <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Process management for avionics. Electronic components capability in operation – Temperature uprating<\/b><\/p>\n |