IEC TR 62240-1:2018 is available as \/2 which contains the International Standard and its Redline version, showing all changes of the technical content compared to the previous edition. IEC TR 62240-1:2018 is a technical report, which provides information when using semiconductor devices in wider temperature ranges than those specified by the device manufacturer. The uprating solutions described herein are considered exceptions, when no reasonable alternatives are available; otherwise devices are utilized within the manufacturers\u2019 specifications. This document describes the methods and processes for implementing this special case of thermal uprating. All of the elements of these methods and processes employ existing, commonly used best engineering practices. No new or unique engineering knowledge is needed to follow these processes, only a rigorous application of the overall approach. The terms \u201cuprating\u201d and \u201cthermal uprating\u201d are being used increasingly in avionics industry discussions and meetings, and clear definitions are included in the present IEC Technical Report. They were coined as shorthand references to a special case of methods commonly used in selecting electronic components for circuit design. This new edition cancels and replaces the first edition published in 2013 and includes a revised wording for subclause 4.1 (Introduction to selection provisions) and the associated flowchart.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 62<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 64<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 67<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 69<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 70<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 74<\/td>\n | 3.2 Abbreviated terms 4 Selection provisions 4.1 General <\/td>\n<\/tr>\n | ||||||
| 75<\/td>\n | Figures Figure 1 \u2013 Flow chart for semiconductor devices over wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 76<\/td>\n | 4.2 Device selection, usage and alternatives 4.2.1 General 4.2.2 Alternatives 4.2.3 Device technology <\/td>\n<\/tr>\n | ||||||
| 77<\/td>\n | 4.2.4 Compliance with the electronic component management plan 4.3 Device capability assessment 4.3.1 General 4.3.2 Device package and internal construction capability assessment 4.3.3 Risk assessment (assembly level) <\/td>\n<\/tr>\n | ||||||
| 78<\/td>\n | 4.3.4 Device uprating methods <\/td>\n<\/tr>\n | ||||||
| 79<\/td>\n | 4.3.5 Device reliability assurance <\/td>\n<\/tr>\n | ||||||
| 80<\/td>\n | 4.4 Device quality assurance (QA) over wider temperature ranges 4.4.1 Decision for the optimum QA method <\/td>\n<\/tr>\n | ||||||
| 81<\/td>\n | 4.4.2 Device level testing 4.4.3 Higher level assembly testing 4.5.1 General 4.5.2 Semiconductor device change monitoring <\/td>\n<\/tr>\n | ||||||
| 82<\/td>\n | 4.6 Final electronic equipment assurance 4.7 Documentation and identification 4.7.1 Documentation 4.7.2 Device identification 4.7.3 Customer notification <\/td>\n<\/tr>\n | ||||||
| 83<\/td>\n | Figure 2 \u2013 Report form for documenting device usage over wider temperature ranges <\/td>\n<\/tr>\n | ||||||
| 84<\/td>\n | Annexes Annex A (informative) Device parameter re-characterisation A.1 Glossary of symbols <\/td>\n<\/tr>\n | ||||||
| 85<\/td>\n | A.2 Rationale for parameter re-characterisation A.2.1 General A.2.2 Assessment for uprateability Figure A.1 \u2013 Parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 86<\/td>\n | A.3 Capability assurance A.3.1 Description A.3.2 Parameter re-characterisation process <\/td>\n<\/tr>\n | ||||||
| 87<\/td>\n | Figure A.2 \u2013 Flow diagram of parameter re-characterisation capability assurance process <\/td>\n<\/tr>\n | ||||||
| 88<\/td>\n | Tables Table A.1 \u2013 Example of sample size calculation <\/td>\n<\/tr>\n | ||||||
| 90<\/td>\n | Figure A.3 \u2013 Margin in electrical parameter measurement based on the results of the sample test <\/td>\n<\/tr>\n | ||||||
| 91<\/td>\n | A.3.3 Application capability assessment Figure A.4 \u2013 Schematic diagram of parameter limit modifications Table A.2 \u2013 Parameter re-characterisation example: SN74ALS244 octal buffer\/driver <\/td>\n<\/tr>\n | ||||||
| 92<\/td>\n | A.4 Quality assurance A.5 Factors to be considered in parameter re-characterisation Figure A.5 \u2013 Parameter re-characterisation device quality assurance <\/td>\n<\/tr>\n | ||||||
| 93<\/td>\n | Figure A.6 \u2013 Schematic of outlier products that can invalidate sample testing <\/td>\n<\/tr>\n | ||||||
| 94<\/td>\n | A.6 Report form for documenting device parameter re-characterisation Figure A.7 \u2013 Example of intermediate peak of an electrical parameter: Voltage feedback input threshold change for Motorola MC34261 power factor controller, see [4] <\/td>\n<\/tr>\n | ||||||
| 95<\/td>\n | Figure A.8 \u2013 Report form for documenting device parameter re-characterisation <\/td>\n<\/tr>\n | ||||||
| 96<\/td>\n | Annex B (informative) Stress balancing B.1 General B.2 Glossary of symbols B.3 Stress balancing B.3.1 General <\/td>\n<\/tr>\n | ||||||
| 97<\/td>\n | B.3.2 Determine the ambient temperature extremes B.3.3 Determine parameter relationship to power dissipation B.3.4 Determine the dissipated power versus ambient temperature relationship <\/td>\n<\/tr>\n | ||||||
| 98<\/td>\n | Figure B.1 \u2013 Iso-TJ curve: Relationship between ambient temperature and dissipated power <\/td>\n<\/tr>\n | ||||||
| 99<\/td>\n | B.3.5 Assess applicability of the method B.3.6 Determine the new parameter values <\/td>\n<\/tr>\n | ||||||
| 100<\/td>\n | B.3.7 Conduct parametric and functional tests B.4 Application example B.4.1 General Figure B.2 \u2013 Graph of electrical parameters versus dissipated power <\/td>\n<\/tr>\n | ||||||
| 101<\/td>\n | B.4.2 Determine the ambient temperature extremes B.4.3 Select the parameters that can be derated <\/td>\n<\/tr>\n | ||||||
| 102<\/td>\n | B.4.4 Construct an Iso-TJ plot B.4.5 Determine whether or not the device can be uprated B.4.6 Determine the new parameter values Figure B.3 \u2013 Iso-TJ curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 103<\/td>\n | B.4.7 Conduct parametric and functional tests B.5 Other notes B.5.1 Margins B.5.2 Cautions and limitations Figure B.4 \u2013 Power versus frequency curve for the Fairchild MM74HC244 <\/td>\n<\/tr>\n | ||||||
| 104<\/td>\n | Figure B.5 \u2013 Flow chart for stress balancing <\/td>\n<\/tr>\n | ||||||
| 105<\/td>\n | Figure B.6 \u2013 Report form for documenting stress balancing <\/td>\n<\/tr>\n | ||||||
| 106<\/td>\n | Annex C (informative) Parameter conformance assessment C.1 General C.2 Test plan C.2.1 General C.2.2 Critical parameters C.2.3 Minimum allowable test margins <\/td>\n<\/tr>\n | ||||||
| 107<\/td>\n | C.2.4 Test options Figure C.1 \u2013 Relationship of temperature ratings, requirements and margins <\/td>\n<\/tr>\n | ||||||
| 109<\/td>\n | Figure C.2 \u2013 Typical fallout distribution versus Treq-max <\/td>\n<\/tr>\n | ||||||
| 110<\/td>\n | C.2.5 Quality assurance <\/td>\n<\/tr>\n | ||||||
| 111<\/td>\n | Figure C.3 \u2013 Parameter conformance assessment flow <\/td>\n<\/tr>\n | ||||||
| 112<\/td>\n | Figure C.4 \u2013 Report form for documenting parameter conformance testing <\/td>\n<\/tr>\n | ||||||
| 113<\/td>\n | Annex D (informative) Higher assembly level testing D.1 General D.2 Process D.2.1 General D.2.2 Analysis of assembly test definition D.2.3 Perform assembly test <\/td>\n<\/tr>\n | ||||||
| 114<\/td>\n | D.2.4 Document results D.2.5 Maintenance notification Figure D.1 \u2013 Flow chart of higher level assembly testing <\/td>\n<\/tr>\n | ||||||
| 115<\/td>\n | Figure D.2 \u2013 Report form for documenting higherlevel assembly test at temperature extremes <\/td>\n<\/tr>\n | ||||||
| 116<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Tracked Changes. Process management for avionics. Electronic components capability in operation – Temperature uprating<\/b><\/p>\n |