{"id":396190,"date":"2024-10-20T04:23:21","date_gmt":"2024-10-20T04:23:21","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1076-2000\/"},"modified":"2024-10-26T08:10:22","modified_gmt":"2024-10-26T08:10:22","slug":"ieee-1076-2000","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1076-2000\/","title":{"rendered":"IEEE 1076-2000"},"content":{"rendered":"

Revision Standard – Superseded. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction
Participants <\/td>\n<\/tr>\n
5<\/td>\nCONTENTS <\/td>\n<\/tr>\n
11<\/td>\n0. Overview of this standard
0.1 Intent and scope of this standard
0.2 Structure and terminology of this standard <\/td>\n<\/tr>\n
12<\/td>\n0.2.1 Syntactic description <\/td>\n<\/tr>\n
13<\/td>\n0.2.2 Semantic description
0.2.3 Front matter, examples, notes, references, and annexes <\/td>\n<\/tr>\n
15<\/td>\n1. Design entities and configurations
1.1 Entity declarations
1.1.1 Entity header <\/td>\n<\/tr>\n
16<\/td>\n1.1.1.1 Generics <\/td>\n<\/tr>\n
17<\/td>\n1.1.1.2 Ports <\/td>\n<\/tr>\n
18<\/td>\n1.1.2 Entity declarative part <\/td>\n<\/tr>\n
19<\/td>\n1.1.3 Entity statement part
1.2 Architecture bodies <\/td>\n<\/tr>\n
20<\/td>\n1.2.1 Architecture declarative part
1.2.2 Architecture statement part <\/td>\n<\/tr>\n
22<\/td>\n1.3 Configuration declarations <\/td>\n<\/tr>\n
23<\/td>\n1.3.1 Block configuration <\/td>\n<\/tr>\n
25<\/td>\n1.3.2 Component configuration <\/td>\n<\/tr>\n
29<\/td>\n2. Subprograms and packages
2.1 Subprogram declarations <\/td>\n<\/tr>\n
30<\/td>\n2.1.1 Formal parameters
2.1.1.1 Constant and variable parameters <\/td>\n<\/tr>\n
31<\/td>\n2.1.1.2 Signal parameter <\/td>\n<\/tr>\n
32<\/td>\n2.1.1.3 File parameters
2.2 Subprogram bodies <\/td>\n<\/tr>\n
35<\/td>\n2.3 Subprogram overloading <\/td>\n<\/tr>\n
36<\/td>\n2.3.1 Operator overloading
2.3.2 Signatures <\/td>\n<\/tr>\n
37<\/td>\n2.4 Resolution functions <\/td>\n<\/tr>\n
38<\/td>\n2.5 Package declarations <\/td>\n<\/tr>\n
39<\/td>\n2.6 Package bodies <\/td>\n<\/tr>\n
41<\/td>\n2.7 Conformance rules <\/td>\n<\/tr>\n
43<\/td>\n3. Types <\/td>\n<\/tr>\n
44<\/td>\n3.1 Scalar types
3.1.1 Enumeration types <\/td>\n<\/tr>\n
45<\/td>\n3.1.1.1 Predefined enumeration types <\/td>\n<\/tr>\n
46<\/td>\n3.1.2 Integer types
3.1.2.1 Predefined integer types
3.1.3 Physical types <\/td>\n<\/tr>\n
48<\/td>\n3.1.3.1 Predefined physical types <\/td>\n<\/tr>\n
49<\/td>\n3.1.4 Floating point types <\/td>\n<\/tr>\n
50<\/td>\n3.1.4.1 Predefined floating point types
3.2 Composite types
3.2.1 Array types <\/td>\n<\/tr>\n
52<\/td>\n3.2.1.1 Index constraints and discrete ranges <\/td>\n<\/tr>\n
54<\/td>\n3.2.1.2 Predefined array types
3.2.2 Record types <\/td>\n<\/tr>\n
55<\/td>\n3.3 Access types <\/td>\n<\/tr>\n
56<\/td>\n3.3.1 Incomplete type declarations <\/td>\n<\/tr>\n
57<\/td>\n3.3.2 Allocation and deallocation of objects
3.4 File types <\/td>\n<\/tr>\n
58<\/td>\n3.4.1 File operations <\/td>\n<\/tr>\n
60<\/td>\n3.5 Protected types
3.5.1 Protected type declarations <\/td>\n<\/tr>\n
61<\/td>\n3.5.2 Protected type bodies <\/td>\n<\/tr>\n
65<\/td>\n4. Declarations
4.1 Type declarations <\/td>\n<\/tr>\n
66<\/td>\n4.2 Subtype declarations <\/td>\n<\/tr>\n
67<\/td>\n4.3 Objects <\/td>\n<\/tr>\n
68<\/td>\n4.3.1 Object declarations
4.3.1.1 Constant declarations <\/td>\n<\/tr>\n
69<\/td>\n4.3.1.2 Signal declarations <\/td>\n<\/tr>\n
70<\/td>\n4.3.1.3 Variable declarations <\/td>\n<\/tr>\n
72<\/td>\n4.3.1.4 File declarations <\/td>\n<\/tr>\n
73<\/td>\n4.3.2 Interface declarations <\/td>\n<\/tr>\n
75<\/td>\n4.3.2.1 Interface lists <\/td>\n<\/tr>\n
76<\/td>\n4.3.2.2 Association lists <\/td>\n<\/tr>\n
78<\/td>\n4.3.3 Alias declarations <\/td>\n<\/tr>\n
79<\/td>\n4.3.3.1 Object aliases <\/td>\n<\/tr>\n
80<\/td>\n4.3.3.2 Nonobject aliases <\/td>\n<\/tr>\n
81<\/td>\n4.4 Attribute declarations <\/td>\n<\/tr>\n
82<\/td>\n4.5 Component declarations
4.6 Group template declarations <\/td>\n<\/tr>\n
83<\/td>\n4.7 Group declarations <\/td>\n<\/tr>\n
85<\/td>\n5. Specifications
5.1 Attribute specification <\/td>\n<\/tr>\n
87<\/td>\n5.2 Configuration specification <\/td>\n<\/tr>\n
88<\/td>\n5.2.1 Binding indication <\/td>\n<\/tr>\n
90<\/td>\n5.2.1.1 Entity aspect <\/td>\n<\/tr>\n
91<\/td>\n5.2.1.2 Generic map and port map aspects <\/td>\n<\/tr>\n
93<\/td>\n5.2.2 Default binding indication <\/td>\n<\/tr>\n
94<\/td>\n5.3 Disconnection specification <\/td>\n<\/tr>\n
97<\/td>\n6. Names
6.1 Names <\/td>\n<\/tr>\n
98<\/td>\n6.2 Simple names <\/td>\n<\/tr>\n
99<\/td>\n6.3 Selected names <\/td>\n<\/tr>\n
101<\/td>\n6.4 Indexed names <\/td>\n<\/tr>\n
102<\/td>\n6.5 Slice names
6.6 Attribute names <\/td>\n<\/tr>\n
105<\/td>\n7. Expressions
7.1 Rules for expressions <\/td>\n<\/tr>\n
106<\/td>\n7.2 Operators
7.2.1 Logical operators <\/td>\n<\/tr>\n
107<\/td>\n7.2.2 Relational operators <\/td>\n<\/tr>\n
108<\/td>\n7.2.3 Shift operators <\/td>\n<\/tr>\n
110<\/td>\n7.2.4 Adding operators <\/td>\n<\/tr>\n
112<\/td>\n7.2.5 Sign operators
7.2.6 Multiplying operators <\/td>\n<\/tr>\n
114<\/td>\n7.2.7 Miscellaneous operators
7.3 Operands <\/td>\n<\/tr>\n
115<\/td>\n7.3.1 Literals <\/td>\n<\/tr>\n
116<\/td>\n7.3.2 Aggregates
7.3.2.1 Record aggregates <\/td>\n<\/tr>\n
117<\/td>\n7.3.2.2 Array aggregates <\/td>\n<\/tr>\n
118<\/td>\n7.3.3 Function calls
7.3.4 Qualified expressions <\/td>\n<\/tr>\n
119<\/td>\n7.3.5 Type conversions <\/td>\n<\/tr>\n
120<\/td>\n7.3.6 Allocators <\/td>\n<\/tr>\n
121<\/td>\n7.4 Static expressions
7.4.1 Locally static primaries <\/td>\n<\/tr>\n
122<\/td>\n7.4.2 Globally static primaries <\/td>\n<\/tr>\n
123<\/td>\n7.5 Universal expressions <\/td>\n<\/tr>\n
125<\/td>\n8. Sequential statements
8.1 Wait statement <\/td>\n<\/tr>\n
127<\/td>\n8.2 Assertion statement <\/td>\n<\/tr>\n
128<\/td>\n8.3 Report statement
8.4 Signal assignment statement <\/td>\n<\/tr>\n
130<\/td>\n8.4.1 Updating a projected output waveform <\/td>\n<\/tr>\n
133<\/td>\n8.5 Variable assignment statement <\/td>\n<\/tr>\n
134<\/td>\n8.5.1 Array variable assignments
8.6 Procedure call statement <\/td>\n<\/tr>\n
135<\/td>\n8.7 If statement
8.8 Case statement <\/td>\n<\/tr>\n
136<\/td>\n8.9 Loop statement <\/td>\n<\/tr>\n
137<\/td>\n8.10 Next statement
8.11 Exit statement <\/td>\n<\/tr>\n
138<\/td>\n8.12 Return statement
8.13 Null statement <\/td>\n<\/tr>\n
139<\/td>\n9. Concurrent statements
9.1 Block statement <\/td>\n<\/tr>\n
140<\/td>\n9.2 Process statement <\/td>\n<\/tr>\n
141<\/td>\n9.3 Concurrent procedure call statements <\/td>\n<\/tr>\n
142<\/td>\n9.4 Concurrent assertion statements <\/td>\n<\/tr>\n
143<\/td>\n9.5 Concurrent signal assignment statements <\/td>\n<\/tr>\n
145<\/td>\n9.5.1 Conditional signal assignments <\/td>\n<\/tr>\n
147<\/td>\n9.5.2 Selected signal assignments <\/td>\n<\/tr>\n
148<\/td>\n9.6 Component instantiation statements <\/td>\n<\/tr>\n
149<\/td>\n9.6.1 Instantiation of a component <\/td>\n<\/tr>\n
151<\/td>\n9.6.2 Instantiation of a design entity <\/td>\n<\/tr>\n
154<\/td>\n9.7 Generate statements <\/td>\n<\/tr>\n
155<\/td>\n10. Scope and visibility
10.1 Declarative region
10.2 Scope of declarations <\/td>\n<\/tr>\n
156<\/td>\n10.3 Visibility <\/td>\n<\/tr>\n
160<\/td>\n10.4 Use clauses
10.5 The context of overload resolution <\/td>\n<\/tr>\n
163<\/td>\n11. Design units and their analysis
11.1 Design units
11.2 Design libraries <\/td>\n<\/tr>\n
164<\/td>\n11.3 Context clauses <\/td>\n<\/tr>\n
165<\/td>\n11.4 Order of analysis <\/td>\n<\/tr>\n
167<\/td>\n12. Elaboration and execution
12.1 Elaboration of a design hierarchy <\/td>\n<\/tr>\n
169<\/td>\n12.2 Elaboration of a block header
12.2.1 The generic clause
12.2.2 The generic map aspect
12.2.3 The port clause
12.2.4 The port map aspect <\/td>\n<\/tr>\n
170<\/td>\n12.3 Elaboration of a declarative part <\/td>\n<\/tr>\n
171<\/td>\n12.3.1 Elaboration of a declaration
12.3.1.1 Subprogram declarations and bodies
12.3.1.2 Type declarations <\/td>\n<\/tr>\n
172<\/td>\n12.3.1.3 Subtype declarations
12.3.1.4 Object declarations <\/td>\n<\/tr>\n
173<\/td>\n12.3.1.5 Alias declarations
12.3.1.6 Attribute declarations
12.3.1.7 Component declarations
12.3.2 Elaboration of a specification
12.3.2.1 Attribute specifications
12.3.2.2 Configuration specifications <\/td>\n<\/tr>\n
174<\/td>\n12.3.2.3 Disconnection specifications
12.4 Elaboration of a statement part
12.4.1 Block statements
12.4.2 Generate statements <\/td>\n<\/tr>\n
176<\/td>\n12.4.3 Component instantiation statements
12.4.4 Other concurrent statements <\/td>\n<\/tr>\n
177<\/td>\n12.5 Dynamic elaboration
12.6 Execution of a model <\/td>\n<\/tr>\n
178<\/td>\n12.6.1 Drivers
12.6.2 Propagation of signal values <\/td>\n<\/tr>\n
181<\/td>\n12.6.3 Updating implicit signals <\/td>\n<\/tr>\n
182<\/td>\n12.6.4 The simulation cycle <\/td>\n<\/tr>\n
185<\/td>\n13. Lexical elements
13.1 Character set <\/td>\n<\/tr>\n
188<\/td>\n13.2 Lexical elements, separators, and delimiters <\/td>\n<\/tr>\n
189<\/td>\n13.3 Identifiers
13.3.1 Basic identifiers
13.3.2 Extended identifiers
13.4 Abstract literals <\/td>\n<\/tr>\n
190<\/td>\n13.4.1 Decimal literals
13.4.2 Based literals <\/td>\n<\/tr>\n
191<\/td>\n13.5 Character literals
13.6 String literals <\/td>\n<\/tr>\n
192<\/td>\n13.7 Bit string literals <\/td>\n<\/tr>\n
193<\/td>\n13.8 Comments <\/td>\n<\/tr>\n
194<\/td>\n13.9 Reserved words <\/td>\n<\/tr>\n
195<\/td>\n13.10 Allowable replacements of characters <\/td>\n<\/tr>\n
197<\/td>\n14. Predefined language environment
14.1 Predefined attributes <\/td>\n<\/tr>\n
211<\/td>\n14.2 Package STANDARD <\/td>\n<\/tr>\n
218<\/td>\n14.3 Package TEXTIO <\/td>\n<\/tr>\n
223<\/td>\nAnnex A (informative) Syntax summary <\/td>\n<\/tr>\n
243<\/td>\nAnnex B (informative) Glossary <\/td>\n<\/tr>\n
261<\/td>\nAnnex C (informative) Potentially nonportable constructs <\/td>\n<\/tr>\n
263<\/td>\nAnnex D (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard VHDL Language Reference Manual<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2000<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":396192,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-396190","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/396190","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/396192"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=396190"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=396190"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=396190"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}