This part of IEC 62878 describes the basics of device embedding substrate.<\/p>\n
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.<\/p>\n
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations 4 Technology of device embedded substrate 4.1 Basic structures <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | Figures Figure 1 \u2013 Examples of device embedded substrate <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4.2 Technology of device embedded substrate Figure 2 \u2013 Completed device embedded substrate (pad connection) Figure 3 \u2013 Completed device embedded substrate (via connection) <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | Figure 4 \u2013 Structure of a pad connection type substrate on a passive device embedded ceramics base Figure 5 \u2013 Structure of a device embedded substrate usinga ceramic board as the base (via connection type) <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | Tables Table 1 \u2013 Classification of device embedding <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 4.3 Structures of device embedded substrates and terms used in this specification Table 2 \u2013 Formed embedded device into the substrate <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | 5 Jisso mounting and interconnection 5.1 General Table 3 \u2013 Embedded device structure and fabrication process <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Table 4 \u2013 Jisso mounting and interconnection of device embedded substrate <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | 5.2 Interconnections and structures of device embedded substrate Figure 6 \u2013 Entire structure of device embedded substrate <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 7 \u2013 Base (typical structure) Figure 8 \u2013 Base (cavity structure) Figure 9 \u2013 Base (insulator) Figure 10 \u2013 Base (Conductive carrier \u2013 metal plate) <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 5.3 Device embedding by conventional process Figure 11 \u2013 Passive device embedded ceramic board used as a base Figure 12 \u2013 Ceramic board used as base (ceramic) Figure 13 \u2013 Wire bonding connection and embedding of active device bare die <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Figure 14 \u2013 Soldering connection and embedding of active device Figure 15 \u2013 Soldering connection of square type passive device Figure 16 \u2013 Conductive resin connection and embedding of active device <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 5.4 Device embedding using vias Figure 17 \u2013 Conductive resin connection and embedding of square type passive device Figure 18 \u2013 Soldering connection into through hole and embedding of passive device Figure 19 \u2013 Connection by copper plating after embedding of active device <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Figure 20 \u2013 Connection by copper plating after embedding of square type passive device Figure 21 \u2013 Conductive paste connection after embedding of active device package Figure 22 \u2013 Conductive paste connection after embeddingof square type passive device chip <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Figure 23 \u2013 Device embedded substrate for device embedding in multi-layers Figure 24 \u2013 Embedding of devices over multiple layers Figure 25 \u2013 Resin base substrate <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | 6 Naming of each section 6.1 General 6.2 General definition of top and bottom surfaces Figure 26 \u2013 Conductor and metal sheet\/copper foil as base substrate Figure 27 \u2013 Device embedded substrate using passive device embedded ceramic substrates as base substrate \u2013 Second type <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | Figure 28 \u2013 Definition of top and bottom surfaces Figure 29 \u2013 Definition of top and bottom surfaces (mounting of a mother board) <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 6.3 Naming of layers and interconnection position Figure 30 \u2013 Names of layers in pad connection <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Figure 31 \u2013 Additional information concerning the interconnection position Figure 32 \u2013 Names of layers in via connection [I] <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Figure 33 \u2013 Names of layers in via connection [II] Figure 34 \u2013 Names of layers in via connection [III] <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | 6.4 Definitions of insulation layer thickness, conductor gap and connection distance between terminal and conductor 6.4.1 General 6.4.2 Insulation layer thickness, conductor gap and electrode\/conductor gap in pad connection Table 5 \u2013 Names of layers of device embedded board <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | 6.4.3 Insulation layer thickness, conductor gap and electrode\/conductor gap in a via connection 6.5 Additional information 6.5.1 Additional information for the insulation layer Figure\u00a035 \u2013 Definition of insulating layer thickness and conductor gap in pad connection Figure 36 \u2013 Definition of electrode gap in via connection <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | 6.5.2 Additional information for conductor gap and electrode\/conductor gap Figure 37 \u2013 Additional illustration of insulating layer thickness Figure 38 \u2013 Additional illustration for conductor gap and electrode\/connector gap <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Device embedded substrate – Guidelines. General description of technology<\/b><\/p>\n |