{"id":80115,"date":"2024-10-17T18:41:05","date_gmt":"2024-10-17T18:41:05","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1394b-2002\/"},"modified":"2024-10-24T19:42:29","modified_gmt":"2024-10-24T19:42:29","slug":"ieee-1394b-2002","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1394b-2002\/","title":{"rendered":"IEEE 1394b 2002"},"content":{"rendered":"

Amendment Standard – Inactive – Superseded. Supplemental information for a high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses is specified. It is intended to extend the usefulness of a low-cost interconnect between external peripherals. This standard follows the IEEE Std 1212 -2001 Command and Status Register (CSR) architecture.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nCover page <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
5<\/td>\nIntroduction <\/td>\n<\/tr>\n
7<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nCONTENTS <\/td>\n<\/tr>\n
13<\/td>\n0. Overview
0.1 Scope <\/td>\n<\/tr>\n
14<\/td>\n0.2 Purpose
0.3 Document organization <\/td>\n<\/tr>\n
15<\/td>\n1. Overview
1.2 References <\/td>\n<\/tr>\n
16<\/td>\n1.5 Service model <\/td>\n<\/tr>\n
17<\/td>\n1.6 Document notation
1.6.1 Mechanical notation
1.6.2 Signal naming <\/td>\n<\/tr>\n
18<\/td>\n1.6.3 Size notation
1.6.4 Numerical values <\/td>\n<\/tr>\n
19<\/td>\n1.6.5 Packet formats
1.6.6 Register formats
1.6.7 C code notation <\/td>\n<\/tr>\n
21<\/td>\n1.6.8 State machine notation
1.6.9 CSR, ROM, and field notation <\/td>\n<\/tr>\n
22<\/td>\n1.6.10 Register specification format <\/td>\n<\/tr>\n
23<\/td>\n1.6.11 Reserved registers and fields <\/td>\n<\/tr>\n
24<\/td>\n1.6.12 Operation description priorities <\/td>\n<\/tr>\n
25<\/td>\n2. Definitions and abbreviations
2.1 Conformance
2.2 Technical glossary <\/td>\n<\/tr>\n
33<\/td>\n2.3 Acronyms and abbreviations <\/td>\n<\/tr>\n
35<\/td>\n3. Summary description
3.10 New features of IEEE Std 1394b-2002
3.10.1 The relationship to IEEE Std 1394a-2000
3.10.2 Faster and further <\/td>\n<\/tr>\n
36<\/td>\n3.10.3 Nomenclature
3.10.4 Media\u2014common properties <\/td>\n<\/tr>\n
38<\/td>\n3.10.5 Arbitration improvements <\/td>\n<\/tr>\n
44<\/td>\n3.10.6 PHY-link interface <\/td>\n<\/tr>\n
45<\/td>\n3.10.7 Miscellaneous features <\/td>\n<\/tr>\n
47<\/td>\n4. Cable PHY specification
4.2.1B Copper PMD cable media attachment <\/td>\n<\/tr>\n
89<\/td>\n9. Short-haul copper PMD electrical specification <\/td>\n<\/tr>\n
90<\/td>\n9.1 Interfaces
9.2 Transmitter electrical specifications <\/td>\n<\/tr>\n
93<\/td>\n9.3 Receiver electrical specifications <\/td>\n<\/tr>\n
94<\/td>\n9.4 Electrical measurements
9.4.1 Transmit rise and fall time
9.4.2 Transmit skew measurement <\/td>\n<\/tr>\n
95<\/td>\n9.4.3 Transmit eye (normalized and absolute)
9.5 DC biasing
9.5.1 Beta-mode receiver bias requirements
9.6 Toning and signal detect <\/td>\n<\/tr>\n
96<\/td>\n9.6.1 Connection tone
9.6.2 PMD signal detect function <\/td>\n<\/tr>\n
98<\/td>\n9.7 Jitter
9.7.1 Jitter specifications <\/td>\n<\/tr>\n
101<\/td>\n10. Glass optical fiber physical medium dependent specification
10.1 PMD block diagram <\/td>\n<\/tr>\n
102<\/td>\n10.2 PMD to MDI optical specifications <\/td>\n<\/tr>\n
103<\/td>\n10.3 Transmitter optical specifications
10.4 Receiver optical specifications <\/td>\n<\/tr>\n
104<\/td>\n10.5 Worst-case connection optical power budget and penalties (informative)
10.6 Optical jitter specifications <\/td>\n<\/tr>\n
106<\/td>\n10.7 Optical measurement requirements
10.7.1 Center wavelength and spectral width measurements
10.7.2 Optical power measurements
10.7.3 Extinction ratio measurements <\/td>\n<\/tr>\n
107<\/td>\n10.7.4 Relative intensity noise (RIN)
10.7.5 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
108<\/td>\n10.7.6 Transmit rise and fall characteristics
10.7.7 Receiver sensitivity measurements
10.7.8 Jitter measurements
10.8 CPR measurement
10.9 Optical connection cabling model <\/td>\n<\/tr>\n
109<\/td>\n10.9.1 Characteristics of the fiber optic medium
10.9.2 Optical fiber and cable
10.9.3 Multimode connector insertion loss
10.9.4 Optical connection return loss
10.10 Optical connection <\/td>\n<\/tr>\n
110<\/td>\n10.11 Fiber launch conditions: OLF <\/td>\n<\/tr>\n
111<\/td>\n11. PMD specification of fiber media with PN connector
11.1 Scope <\/td>\n<\/tr>\n
112<\/td>\n11.2 PMD block diagram
11.3 Cables <\/td>\n<\/tr>\n
113<\/td>\n11.4 Connector
11.5 Connector and cable assembly performance criteria <\/td>\n<\/tr>\n
114<\/td>\n11.6 Optical fiber interface <\/td>\n<\/tr>\n
115<\/td>\n11.7 Optical jitter specifications <\/td>\n<\/tr>\n
116<\/td>\n11.8 Permitted number of segments (informative) <\/td>\n<\/tr>\n
119<\/td>\n12. CAT-5 UTP PMD specification
12.1 Overview <\/td>\n<\/tr>\n
120<\/td>\n12.2 PMD block diagram
12.3 Operation of CAT-5 connections
12.4 Media specification <\/td>\n<\/tr>\n
121<\/td>\n12.4.1 100 W UTP connection segment specification
12.4.2 100 W UTP cable specification
12.4.3 Connection hardware
12.4.4 Media interface connector <\/td>\n<\/tr>\n
122<\/td>\n12.4.5 Autocrossover
12.5 PMD electrical specifications
12.5.1 Galvanic isolation
12.5.2 Transmitter specifications <\/td>\n<\/tr>\n
124<\/td>\n12.5.3 Receiver specifications <\/td>\n<\/tr>\n
126<\/td>\n12.6 PMD implementation (informative) <\/td>\n<\/tr>\n
127<\/td>\n13. Beta-mode port specification
13.1 Overview <\/td>\n<\/tr>\n
128<\/td>\n13.2 Port functions
13.2.1 Overview <\/td>\n<\/tr>\n
129<\/td>\n13.2.2 Naming conventions <\/td>\n<\/tr>\n
130<\/td>\n13.2.3 Control mapping
13.2.4 Request types <\/td>\n<\/tr>\n
132<\/td>\n13.2.5 Scrambling <\/td>\n<\/tr>\n
136<\/td>\n13.2.6 Coding <\/td>\n<\/tr>\n
144<\/td>\n13.2.7 Character transmission
13.2.8 Decoding <\/td>\n<\/tr>\n
145<\/td>\n13.2.9 Receiver running disparity
13.2.10 Descrambling
13.3 Beta-mode port operation
13.3.1 Transmit operations <\/td>\n<\/tr>\n
149<\/td>\n13.3.2 Receive operations <\/td>\n<\/tr>\n
152<\/td>\n13.4 Beta port state machines <\/td>\n<\/tr>\n
153<\/td>\n13.4.1 Port transmit state machine <\/td>\n<\/tr>\n
154<\/td>\n13.4.2 Port receive state machine <\/td>\n<\/tr>\n
157<\/td>\n14. Connection management
14.1 Overview <\/td>\n<\/tr>\n
158<\/td>\n14.2 Port characteristics
14.2.1 Requirements
14.2.2 Properties <\/td>\n<\/tr>\n
159<\/td>\n14.3 Functions, variables, and constants <\/td>\n<\/tr>\n
161<\/td>\n14.4 Port controller
14.5 Port connection manager state machine <\/td>\n<\/tr>\n
166<\/td>\n14.6 Standby
14.6.1 Nephew node characteristics
14.6.2 Uncle node characteristics <\/td>\n<\/tr>\n
167<\/td>\n14.7 Loop prevention <\/td>\n<\/tr>\n
168<\/td>\n14.7.1 Test port
14.7.2 Loop test data (LTD) <\/td>\n<\/tr>\n
169<\/td>\n14.7.3 HR
14.7.4 Maximum occupancy timer
14.7.5 Loop-test symbol (LTS) <\/td>\n<\/tr>\n
170<\/td>\n14.7.6 Loop-test packet (LTP)
14.7.7 Test port selection
14.7.8 Loop test <\/td>\n<\/tr>\n
171<\/td>\n14.7.9 Completing the attach
14.7.10 Received ATTACH_REQUEST or bus reset <\/td>\n<\/tr>\n
172<\/td>\n14.7.11 Loop Disabled state
14.7.12 Connections to Legacy nodes
14.7.13 Loop detection during bus initialization
14.7.14 Minimal LTP support
14.7.15 Isolated node behavior <\/td>\n<\/tr>\n
173<\/td>\n14.8 Connection management
14.8.1 Connection detection
14.8.2 Connection detection and mode determination algorithm <\/td>\n<\/tr>\n
174<\/td>\n14.8.3 Beta-mode speed negotiation <\/td>\n<\/tr>\n
176<\/td>\n14.8.4 Disabled ports <\/td>\n<\/tr>\n
177<\/td>\n15. PHY register map
15.1 PHY register map for the cable environment <\/td>\n<\/tr>\n
180<\/td>\n15.1.1 Port Status page <\/td>\n<\/tr>\n
183<\/td>\n15.1.2 Vendor Identification page <\/td>\n<\/tr>\n
184<\/td>\n15.2 Integrated link and PHY <\/td>\n<\/tr>\n
185<\/td>\n16. Data routing, arbitration, and control
16.1 Overview <\/td>\n<\/tr>\n
186<\/td>\n16.2 PHY services
16.2.1 Cable PHY bus management services for the management layer <\/td>\n<\/tr>\n
188<\/td>\n16.2.2 PHY arbitration services for the link layer <\/td>\n<\/tr>\n
191<\/td>\n16.2.3 PHY data services for the link layer <\/td>\n<\/tr>\n
192<\/td>\n16.2.4 PHY-link interface block <\/td>\n<\/tr>\n
193<\/td>\n16.2.5 PMD services for the PHY <\/td>\n<\/tr>\n
196<\/td>\n16.3 PHY facilities
16.3.1 Packet formats <\/td>\n<\/tr>\n
200<\/td>\n16.3.2 Packet forwarding <\/td>\n<\/tr>\n
201<\/td>\n16.3.3 Cable PHY packets <\/td>\n<\/tr>\n
206<\/td>\n16.3.4 Cable interface timing constants <\/td>\n<\/tr>\n
208<\/td>\n16.4 Cable PHY operation
16.4.1 C code functions and variables <\/td>\n<\/tr>\n
210<\/td>\n16.4.2 Beta-mode arbitration <\/td>\n<\/tr>\n
212<\/td>\n16.4.3 Hybrid bus operation <\/td>\n<\/tr>\n
216<\/td>\n16.4.4 Isochronous intervals <\/td>\n<\/tr>\n
219<\/td>\n16.4.5 Bus reset state machine <\/td>\n<\/tr>\n
220<\/td>\n16.4.6 Tree identification state machine <\/td>\n<\/tr>\n
222<\/td>\n16.4.7 Self-identification state machine <\/td>\n<\/tr>\n
225<\/td>\n16.4.8 Arbitration state machine <\/td>\n<\/tr>\n
229<\/td>\n17. B PHY- link interface (parallel)
17.1 B PHY-link interface characteristics <\/td>\n<\/tr>\n
230<\/td>\n17.2 PHY-link interface signals
17.2.1 Interface signal descriptions <\/td>\n<\/tr>\n
232<\/td>\n17.3 Interface initialization, reset, and disable
17.3.1 LPS signal characteristics <\/td>\n<\/tr>\n
233<\/td>\n17.3.2 Interface reset <\/td>\n<\/tr>\n
234<\/td>\n17.3.3 Interface disable
17.3.4 Restoration and initialization <\/td>\n<\/tr>\n
236<\/td>\n17.4 Link-on and interrupt indications
17.4.1 LinkOn signal characteristics <\/td>\n<\/tr>\n
237<\/td>\n17.5 Link requests and notifications
17.5.1 Link request characteristics <\/td>\n<\/tr>\n
240<\/td>\n17.5.2 Link notifications <\/td>\n<\/tr>\n
241<\/td>\n17.5.3 Link request and notification format <\/td>\n<\/tr>\n
243<\/td>\n17.6 Interface data transfers
17.6.1 Interface phases
17.6.2 Packet reception <\/td>\n<\/tr>\n
245<\/td>\n17.6.3 Packet transmission <\/td>\n<\/tr>\n
250<\/td>\n17.7 Format of received and transmitted data
17.7.1 S100 data <\/td>\n<\/tr>\n
251<\/td>\n17.7.2 S200 data
17.7.3 S400 data
17.7.4 S800 data <\/td>\n<\/tr>\n
252<\/td>\n17.8 Status transfers and notifications from the PHY
17.8.1 Bus Status Transfers <\/td>\n<\/tr>\n
253<\/td>\n17.8.2 PHY Status Transfers <\/td>\n<\/tr>\n
255<\/td>\n17.9 Delays affecting interoperability of PHYs and links <\/td>\n<\/tr>\n
256<\/td>\n17.10 Legacy link support <\/td>\n<\/tr>\n
257<\/td>\n17.11 Electrical characteristics
17.11.1 DC signal levels and waveforms <\/td>\n<\/tr>\n
258<\/td>\n17.11.2 AC timing <\/td>\n<\/tr>\n
260<\/td>\n17.11.3 Isolation barrier (informative) <\/td>\n<\/tr>\n
262<\/td>\n17.11.4 Alternative isolation barrier (informative) <\/td>\n<\/tr>\n
265<\/td>\n18. PIL-FOP serial interface
18.1 Operating model <\/td>\n<\/tr>\n
266<\/td>\n18.2 PIL-FOP connection management
18.2.1 Power-on
18.2.2 PIL-FOP negotiation <\/td>\n<\/tr>\n
267<\/td>\n18.2.3 PIL-FOP restore
18.2.4 Port restore
18.2.5 Loss of synchronization
18.2.6 Loss of power
18.2.7 LPS <\/td>\n<\/tr>\n
268<\/td>\n18.2.8 Serial Bus reset
18.3 Serial Bus configuration request types not carried over the PIL-FOP interface
18.4 P2P packet protocol <\/td>\n<\/tr>\n
271<\/td>\n19. C code
19.1 Common declarations and functions <\/td>\n<\/tr>\n
285<\/td>\n19.2 Connection management routines
19.2.1 Node-level connection monitor <\/td>\n<\/tr>\n
293<\/td>\n19.2.2 Port connection manager actions and conditions <\/td>\n<\/tr>\n
307<\/td>\n19.3 Port state machine actions
19.3.1 DS port <\/td>\n<\/tr>\n
313<\/td>\n19.3.2 Beta port <\/td>\n<\/tr>\n
326<\/td>\n19.4 Border arbitration actions and conditions
19.4.1 Border arbitration functions <\/td>\n<\/tr>\n
345<\/td>\n19.4.2 Request processing <\/td>\n<\/tr>\n
353<\/td>\n19.4.3 Bus reset <\/td>\n<\/tr>\n
356<\/td>\n19.4.4 Tree identification <\/td>\n<\/tr>\n
357<\/td>\n19.4.5 Self-identification <\/td>\n<\/tr>\n
361<\/td>\n19.5 Border arbitration <\/td>\n<\/tr>\n
373<\/td>\nAnnex K\u2014Serial Bus cable test procedures <\/td>\n<\/tr>\n
377<\/td>\nAnnex O\u2014Jitter measurements <\/td>\n<\/tr>\n
379<\/td>\nAnnex P\u2014Connection status change <\/td>\n<\/tr>\n
381<\/td>\nAnnex Q\u2014Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Standard for High Performance Serial Bus (High Speed Supplement)]<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2002<\/td>\n381<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80116,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80115","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80115","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80116"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80115"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80115"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80115"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}