{"id":81072,"date":"2024-10-17T18:51:00","date_gmt":"2024-10-17T18:51:00","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-6-2003\/"},"modified":"2024-10-24T19:45:36","modified_gmt":"2024-10-24T19:45:36","slug":"ieee-1149-6-2003","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-6-2003\/","title":{"rendered":"IEEE 1149.6 2003"},"content":{"rendered":"
New IEEE Standard – Active. his standard augments IEEE Std 1149.1 to improve the ability for testing differential and\/or ac-coupled interconnections between integrated circuits on circuit boards and systems.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Introduction Participants <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1. Overview 1.1 Scope 1.2 Organization of the standard <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 1.3 Context <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1.4 Objectives 2. References 3. Definitions and acronyms 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 3.2 Acronyms <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 4. Technology 4.1 Signal pin types 4.2 Signal coupling and coupling combinations <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.3 The effects of defects <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 4.4 Defects targeted by the standard <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 4.5 Differential termination and testability <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 4.6 Test signal implementation <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 4.7 Test receiver support for AC testing instructions <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 4.8 Test receiver support for the (DC) EXTEST instruction <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 4.9 A general test receiver for DC and AC testing instructions <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 4.10 Boundary-Scan capture data versus configuration <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 4.11 Noise sources and sensitivities <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 5. Instructions 5.1 IEEE Std 1149.1 instructions 5.2 AC testing instructions <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 5.3 The EXTEST_PULSE instruction <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 5.4 The EXTEST_TRAIN instruction <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | 5.5 AC Test Signal generation 6. Pin implementation specifications 6.1 Pin identification <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 6.2 Input test receivers <\/td>\n<\/tr>\n | ||||||
67<\/td>\n | 6.3 Output drivers <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | 6.4 Bidirectional pins <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 6.5 AC\/DC selection cells <\/td>\n<\/tr>\n | ||||||
75<\/td>\n | 7. Conformance and documentation requirements 7.1 Conformance <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | 7.2 Documentation <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | 7.3 BSDL package for Advanced I\/O description (STD_1149_6_2003) <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | 7.4 BSDL extension structure <\/td>\n<\/tr>\n | ||||||
82<\/td>\n | 7.5 BSDL attribute definitions <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 7.6 Example BSDL <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | Annex A <\/td>\n<\/tr>\n | ||||||
114<\/td>\n | Annex B <\/td>\n<\/tr>\n | ||||||
117<\/td>\n | Annex C <\/td>\n<\/tr>\n | ||||||
123<\/td>\n | Annex D <\/td>\n<\/tr>\n | ||||||
135<\/td>\n | Annex E <\/td>\n<\/tr>\n | ||||||
138<\/td>\n | Annex F <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks<\/b><\/p>\n |